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FAN7310
LCD Back Light Inverter Drive IC
Features
* * * * * * * * * * High Efficiency Single Stage Power Conversion Wide Input Voltage Range 5V to 24V Back Light Lamp Ballast and Soft Dimming Reduce External Components Precision Voltage Reference Trimmed to 2% ZVS full-bridge topology Soft Start PWM Control at fixed frequency Analog and Burst Dimming Function Synchronizable Switching Frequency With An External Signal * Open Lamp Protection * Open Lamp Regulation * 20 Pin SSOP
Description
The FAN7310 provides all the control functions for a series parallel resonant converter and also contains a pulse width modulation (PWM) controller to develop a supply voltage. Typical operating frequency range is between 30kHz and 250kHz depending on the CCFL and the transformer's characteristics. The FAN7310 has a patent-pending on new phase-shift control.
20-SSOP
1
Rev. 1.0.1
(c)2004 Fairchild Semiconductor Corporation
FAN7310
Internal Block Diagram
RT max. 2V min. 0.5V
OSCILLATOR Output Driver
OUTA
OUTB CT SYNC S_S + + Output Control Logic Output Driver OUTD EA_OUT 6uA S_S ADIM EA_IN Solr Error Amp. + + 105uA Solr Voltage Reference & Internal Bias 2.5VREF 2V REF 1.4uA UVLO
Q
SET
PGND OUTC
+
S
OLP 2V 2.7V
Q
CLR
R
UVLO + OLR
Sburst 85uA max. 2V min. 0.5V BCT BDIM AGND Sburst + UVLO
ENA 1.4V VIN VIN UVLO 5V
2
FAN7310
Pin Assignments
SYNC
OUTB
OUTA
VIN
PGND
OUTC
OUTD
CT
RT
BCT
20
19
18
17
16
15
14
13
12
11
FAN7310
1
OLP
2
OLR
3
ENA
4
S_S
5
GND
6
REF
7
ADIM
8
BDIM
9
10
EA_IN EA_OUT
Pin Definitions
No 1 2 3 4 5 6 7 8 9 10 Name OLP OLR ENA S_S GND REF ADIM BDIM EA_IN EA_OUT Function Description Open Lamp Protection Open Lamp Regulation Enable Input Soft Start Analog Ground 2.5V Reference Voltage Analog Dimming Input Burst Dimming Input Error Amplifier Input Error Amplifier Output No 11 12 13 14 15 16 17 18 19 20 Name BCT RT CT OUTD OUTC PGND VIN OUTA OUTB SYNC Function Description Burst Dimming Timing Capacitor Timing Resistor Timing Capacitor NMOSFET Drive Output D PMOSFET Drive Output C Power Ground Supply Voltage PMOSFET Drive Output A NMOSFET Drive Output B Sychronization Input/Output
3
FAN7310
Absolute Maximum Ratings
For typical values Ta=25C, Vcc=12V and for min/max values Ta is the operating ambient temperature range with -25C Ta 85C and 5V Vcc 24V, unless otherwise specified. Characteristics Supply Voltage Operating Temperature Range Storage Temperature Range Thermal Resistance Junction-Air (Note1,2) Power Dissipation
Note: 1. Thermal resistance test board Size: 76.2mm * 114.3mm * 1.6mm(1S0P) JEDEC standard: JESD51-3, JESD51-7 2. Assume no ambient airflow
Symbol VCC Topr Tstg RJA Pd
Value 5 ~ 24 -25 ~ 85 -65 ~ 150 112 1.1
Unit V C C C/W W
4
FAN7310
Electrical Characteristics
For typical values Ta=25C, Vcc=12V and for min/max values Ta is the operating ambient temperature range with -25C Ta 85C and 5V Vcc 24V, unless otherwise specified. Characteristics REFERENCE SECTION Line Regulation 2.5V Regulation Voltage OSCILLATOR SECTION(MAIN) Oscillation Frequency CT High Voltage CT Low Voltage OSCILLATOR SECTION(BURST) Oscillation Frequency BCT High Voltage BCT Low Voltage ERROR AMP SECTION Open Loop Gain Unit Gain Bandwidth Feedback Output High Voltage Output Sink Current Output Source Current EA_IN Driving Current On OLR EA_IN Driving Current On Burst Dimming Feedback High Voltage On Burst Dimming SOFT START SECTION Soft Start Current Soft Start Clamping Voltage PROTECTION SECTION Open Lamp Protection Voltage Open Lamp Regulation Voltage Open Lamp Protection Charging Current UNDER VOLTAGE LOCK OUT SECTION Start Threshold Voltage Start Up Current Operating Supply Current Stand-by Current ON/OFF SECTION On State Input Voltage Off Stage Input Voltage Von Voff 2 5 0.7 V Vth Ist Iop Isb VCC = 12V VCC = 12V VCC = Vth-0.2 130 1.5 200 5 V uA mA uA Volp Volr Iolp 1.75 1.75 0.7 2 2 1.4 2.25 2.25 2.1 V V ISS Vssh S_S=2V 4 6 5 8 uA V Veh lsin lsur Iolr Iburst Vfbh R(EA_IN) = 60k EA_IN = 0V EA_OUT = 1.5V EA_OUT = 1.5V 1 75 61 80 1.5 2.5 105 85 -1 135 109 dB MHz V mA mA uA uA V fosc Vbcth Vbctl Ctb = 10nF, Rt=18k 195 225 2 0.5 255 Hz V V fosc Vcth Vctl Ta = 25C, Ct = 270pF Rt = 18k Ct = 270pF, Rt = 18k 108 106 115 115 2.0 0.5 122 124 V V kHz Vref V25 5 VCC 24V 2.45 2 2.5 25 2.55 mV V Symbol Test Condition Min. Typ. Max. Unit
Va+0.1 Va+0.4 Va+0.7
5
FAN7310
Electrical Characteristics (Continued)
For typical values Ta=25C, Vcc=12V and for min/max values Ta is the operating ambient temperature range with -25C Ta 85C and 5V Vcc 24V, unless otherwise specified. Characteristics OUTPUT SECTION PMOS Gate High Voltage PMOS Gate Low Voltage NMOS Gate Drive Volgate NMOS Gate Drive Volgate PMOS Gate Voltage With UVLO Activated NMOS Gate Voltage With UVLO Activated Rising Time Falling Time MAX./MIN OVERLAP Min. Overlap between diagonal switches Max. Overlap betwwen diagonal switches DELAY TIME PDR_A/NDR_B PDR_C/NDR_D Rt=18k Rt=18k 450 450 ns ns fosc=100KHz fosc=100KHz 0 100 % % Vpdhv Vphlv Vndhv Vndhv Vpuv Vnuv Tr Tf VCC = 12V VCC = 12V VCC = 12V VCC = 12V VCC = Vth-0.2 VCC = Vth-0.2 VCC = 12V VCC = 12V 6 Vcc-0.3 Vcc 8.5 0 200 200 10.5 0.3 500 500 V V ns ns V V Vcc-10.5 Vcc-8.5 Vcc-6 Symbol Test Condition Min. Typ. Max. Unit
6
FAN7310
Function Description
UVLO : The under voltage lockout circuit guarantees stable operation of the IC's control circuit by stopping and starting it as a function of the Vin value. The UVLO circuit turns on the control circuit when Vin exceeds 5V. When Vin is lower than 5V, the IC's standby current is less than 200uA. ENA : Applying the voltage higer than 2V to ENA pin enables the operation of the IC. Applying to the voltage lower than 0.7V to ENA pin will disable the operation of the inverter. Soft start :The soft start function is provided that S_S pin is connected through a capacitor to GND. A soft start circuit ensures a gradual increase in the input and output power. The capacitor connected to S_S pin determines the rate of rise of the duty ratio. It is charged by a current source of 6uA.
Burst oscillator & burst dimming :Timing capacitor BCT are charged by the reference current source, formed by the timing resistor Rt whose voltage is regulated at 1.25V. The sawtooth waveform charges up to 2V. Once reached, capacitors begin discharging down to 0.5V. Next timing capacitors start charging again and a new switching cycle begins. The burst dimming frequency can be programmed with adjusting the values of Rt and BCT. The burst dimming frequency can be calculated as below.
3.75 f burst = ---------------------------------64 R BC T T
The burst dimming frequency should be greater than 120Hz to avoid visible flicker. To compare the input of BDIM pin with the 0.5~2V triangular wave of burst oscillator makes the PWM pulse for burst dimming. The PWM pulse controls EA_OUT's voltage by summing 85uA into EA_IN pin.
Main oscillator : Timing capacitor CT are charged by the reference current source, formed by the timing resistor Rt whose voltage is regulated at 1.25V. The sawtooth waveform charges up to 2V. Once reached, capacitors begin discharging down to 0.5V. Next timing capacitors start charging again and a new switching cycle begins. The main frequency can be programmed with adjusting the values of Rt and CT. The main frequency can be calculated as below.
19 f op = -----------------------------32 R T C T
7
FAN7310
Open lamp regulation & open lamp protection : It is necessary to suspend power stage operation if an open lamp occurs, because the power stage has high gain. When a voltage higher than 2V is applied to the OLR pin, the part enters the regulation mode and controls EA_OUT voltage to limit the lamp voltage by summing 105uA into the feedback node. At the same time, the OLP capacitor, connected to the OLP pin, is charged by the 1.4uA internal current source. Once reached to 2V, IC enters shut down where all the output is high.
OUTPUT DRIVES: The four output drives are designed so that switches A and B, C and D never turn on simultaneously. The OUTA-OUTB pair is intended to drive one half-bridge in the external power stage. The OUTC-OUTD pair will drive the other half-bridge.
SYNC: This pin is used as the frequency synchronization. The switching frequency can be synchronized with an external control signal.
8
FAN7310
Timing Diagram
FAN7310 use the improved phase-shfit control full-brdige to drive CCFL. As a result, the temperature difference between the left leg and the right legs is almost zero. The detail timing is shown as bellow.
EA_OUT CT
SYNC
T
T1
POUT A
NOUT B
POUT C
NOUT D
9
FAN7310
Typical Application Circuit
VCC
C25 100u C26 1u R6 OLP SYNC 100k OLR R24 OUTB OUTA VIN C6 1u GND C2 REF 1u R4 22k R2 56k ADIM BDIM C21 10n R3 20k C3 EA_OUT BCT EA_IN OUTD CT R5 27k RT C4 6.8n OUTD C5 220p REF PGND OUTC OUTC OUTB OUTA M1 FDS8958A C7 10u M2 FDS8958A R25 10k R26
IC1 FAN7310
C27 1u
C22 1u
0
0
0
10k
0
ENA
ENA 10k C28 10n
0
C1 1u
S_S
0 0
TX1
0
REF
0 0
DIM(0~3.3V)
0 0 0 0
R15 FB 2k R9 8.2k
0
C10 15p OLP1
CCFL
0
OLR FB D4 BAV99 D6 BAV99 R16 1.5k
0
0
4.7n R8
C14 20n
100k
0
0
0
0
0
OLR R14 100k OLP1 OLP R1 330k R22 10k C16 2.2n
0
0
C9 1u
Q1 KST2222 D1 D1N4148
D11 D1N4148
C19 2.2n
0
0
10
FAN7310
Mechanical Dimensions
Package Dimensions in millimeters
20-SSOP
11
FAN7310
Ordering Information
Product number FAN7310G Package 20-SSOP Operating Temperature -25C ~ 85C
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 10/6/04 0.0m 001 Stock#DSxxxxxxxx (c) 2004 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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